A random access memory ("RAM") array is basically constructed of memory cells as storage units arranged at the intersections of a plurality of word lines arranged in the row direction and a plurality of bit lines (also called digit lines) arranged in the column direction. Among the plurality of word lines, only one word line is set at a selected level and the memory cells coupled to the selected word line are enabled so as to output data to the bit lines from the enabled memory cells during a read cycle, and the data is forced from the write driver to the bit lines into the enabled memory cells in a write cycle. Thus, the word line driver circuit is one of the most crucial circuits in a memory array. If the word line driver circuits are not completely reliable, then there is the possibility that word lines may be erroneously selected resulting in the reading and writing of erroneous data.
Essentially, when a word line goes valid (e.g., a "high" voltage level is placed on the word line by the driver circuit), a memory cell(s) is selected. When the word line is turned off (e.g., a ground voltage potential is placed on the word line), then the memory cell(s) is deselected.
Referring to FIG. 2, there is illustrated a prior art word line driver circuit. Signals IN1 and IN2 are the two inputs of the circuit and signal WL is the output. Signals IN1 and IN2 may be the decoded row address for accessing memory cells. This word line driver circuit has four operational states:
(1) When signal IN1 is low and signal IN2 is high, the circuit is in a "deselected" operational state (output signal WL is not activated). In this instance, node 210 is driven high and signal WL is set to GND (ground voltage potential). P-channel field-effect transistor ("FET") 204 is switched on pulling node 211 to a voltage potential supplied by voltage supply VDD. This causes node 212 to have a ground potential. Node 213 is caused to go to a voltage potential of VDD minus the threshold voltage across n-channel FET device 206. PA1 (2) Both signals IN1 and IN2 are low. This results in the same "deselected" operational state as in (1) above, except that node 211 is now floating high. PA1 (3) Both signals IN1 and IN2 are high. This causes node 210 to be at a high potential (VDD), which forces output signal WL to be low. Device 204 turns on, which causes node 211 to have a high potential and causes node 212 to have a ground potential. PA1 (4) Input signal IN1 is high and input signal IN2 is low, resulting in a "selected" operational state of the driver circuit (i.e., output signal WL is activated). This forces node 210 to a ground potential resulting in a high potential signal at output WL. If output WL is high, this causes n-channel device 206 to turn on, or to become conducting, and also causes device 204 to turn off. The low state of signal IN2 turns device 205 off. With both devices 204 and 205 off, node 211 is in a floating state. During a long cycle (often greater than 300 MHz), isolated node 211 will float towards a ground potential causing device 201 to conduct. In this situation, signal IN2 is trying to pull node 210 to a ground potential while device 201 is trying to pull node 210 to a high (VDD) potential. At the same time that node 211 is floating towards a ground potential, inverter 209 turns on, forcing node 212 to a VDD potential, which turns on device 207. This results in device 207 trying to pull output signal WL towards a ground potential, while inverter 208 is trying to keep signal WL at a VDD potential. These conditions will cause output signal WL to oscillate. Oscillations in the driver circuit result in increased power consumption.
U.S. Pat. Nos. 4,951,259, 4,610,002, 4,195,238, and 3,980,899 disclose driver circuits that prevent the output word line signal WL from floating. However, none of these disclosed circuits teaches a word line driver circuit containing no floating internal nodes. Floating internal nodes may cause oscillations of the driver circuit.